This invention pertains to a liquid crystal display device, driving methods for liquid crystal display devices, inspection methods for electrical properties of liquid crystal display devices; and, in particular, liquid crystal display devices such as those in which transistors are formed on a liquid crystal matrix substrate for the purpose of driving a liquid crystal matrix.
In an active matrix liquid crystal display device using thin film transistors (abbreviated as TFTs in the remainder of this document) as the switching elements, if it is possible to form the active matrix driving circuits from TFTs and fabricate those TFTs at the same time as the picture element (pixel) TFTs on the active matrix substrate, the need to provide driver ICs is removed; and this is convenient.
Compared to transistors integrated on single crystal silicon, however, the operating speeds of TFTs are slow and there is a definite limit to the increase in driving circuit speed attainable. Additionally, if the driving circuits are made to operate at high speeds, the power consumption will increase by that much more.
As examples of technology for operating driving circuits of liquid crystal display devices at high speed, there is the technology in Japanese Unexamined Patent Application Showa 61-32093 and the technology in pages 609-612 of the SID Digest (1992).
In the technology described in Japanese Unexamined Patent Application Showa 61-32093, the driving circuits are composed of multiple shift registers and, by driving each shift register by clocks with slightly different phases, the effective operating frequency of the shift registers is increased.
In the SID Digest (1992), pages 609-612, technology in which multiple analog switches are driven collectively by a single output of a timing control circuit and the video signal is written in parallel is shown.
As examples of technology striving for reduced power consumption in driving circuits, there is the technology contained in Japanese Unexamined Patent Application Showa 61-32093. This technology achieves reduced power consumption by dividing the driving circuits into multiple blocks and operating only blocks which must be used while keeping all other blocks out of operation.
When actually implementing the technology described in Japanese Unexamined Patent Application 61-32093, however, it is necessary to provide multiple clocks with differing phases which leads to increased complexity of the circuit configurations and an increase in the number of terminals.
Further, in the technology described in the SID Digest (1992), pages 609-612, because multiple analog switches are driven collectively, the load is heavy and it is necessary to provide a buffer which can drive a heavy load. Additionally, because of delays in the driving signals, it is easy for deviations to occur in the driving timing of each analog switch.
In the technology of Japanese Unexamined Patent Application 61-32093, a control circuit is necessary in order to selectively operate the divided blocks; and this leads to increased complexity of the circuitry. Additionally, this technology does not contribute at all to increasing the speed of the driving circuits.
Furthermore, when the driving circuits of the prior art described above are composed of TFTs, the circuits become complex in all cases; and the accurate, fast inspection of the circuits electrical characteristics is difficult such that there are problems in the evaluation of reliability.